What will computer chips look like in 2045?

Episode Overview

• Dwarkesh Patel speaks with Intel engineers and leaders Chris Auth, Kevin Fischer, Jack Kavalieros, Tyler Osborn, and Pushkar Ranade about how leading-edge semiconductor chips are manufactured, how Intel is working to catch up to TSMC, and how physical supply-chain bottlenecks are shaping the future of AI.
• The episode traces the evolution of chipmaking from Intel's multi-year stumbles on the 10-nanometer node to the current race for 18A and 14A, explaining the physics of Gate-All-Around transistors, backside power delivery, and $400 million High-NA EUV lithography machines.
• Inside the research labs and factories, the guests break down how engineers hunt microscopic defects across 2,000 processing steps, explore new materials like ruthenium to replace copper wires at the atomic scale, and fuse multiple chips together using advanced hybrid bonding.
• The conversation concludes with a macro analysis of the semiconductor supply chain, revealing why infinite capital cannot quickly multiply leading-edge wafer production and why AI hyperscalers and figures like Elon Musk are moving toward building dedicated foundry capacity.

Key Concepts

• The Complexity vs. Schedule Trap (Lessons from 10nm): Manufacturing a modern wafer requires roughly 2,000 sequential steps that must run repeatably across thousands of wafers per week. On its 10nm node (originally targeted for 2016, but delayed until 2018), Intel attempted "hyperscaling" without waiting for Extreme Ultraviolet (EUV) lithography tools, which print using a 13.5 nm light wavelength (about 14x shorter than the previous 193 nm tools). Meanwhile, TSMC put EUV into volume production in 2019 and ramped it on 5nm in 2020, gaining a roughly four-year lead in EUV experience before Intel's first EUV node reached products in 2023. Intel's takeaway was that packing too much innovation into one node destroys schedule predictability.
• Transistor Evolution and the Post-Dennard Materials Explosion: As planar transistors shrank, the source and drain grew so close that current leaked when the switch was off. To maintain electrostatic control, the industry moved from Planar transistors (gate touching the channel on 1 side) to FinFETs (vertical fin touched on 3 sides, demonstrated in 1989 and put into volume production by Intel in 2011) to Gate-All-Around or GAA (horizontal nanoribbons wrapped on all 4 sides, demonstrated in 1988 and produced by Samsung in 2022). Manufacturing GAA requires sandwiching silicon with temporary placeholder layers because final metal gate materials cannot survive subsequent 1,000°C baking steps. Because classic Dennard scaling and clock speeds plateaued around ~3.7 GHz in 2004, progress shifted to materials science, increasing the number of periodic table elements used or evaluated in chips from 12 in the 1980s and 16 in the 1990s to roughly 60 by the 2000s.
• Why High-NA EUV and Backside Power Are Linked: Standard EUV has a Numerical Aperture (NA) of 0.33 and costs ~$200 million per machine; High-NA EUV widens the light cone to 0.55, printing features ~1.7x smaller in a single pass, but costs ~$400 million. High-NA makes economic sense for Intel's 14A node (where it is offered as an option in the Process Design Kit, as it adds some complexity) because Intel uses "backside power," moving thick power delivery wires to the bottom of the wafer and leaving only thin signal wires on top. This relaxes the front-side wire spacing ("pitch") just enough for High-NA to print in a single pass. Because TSMC does not use backside power on its equivalent node, its front-side pitches remain too tight even for High-NA, forcing multi-patterning (splitting a pattern across multiple passes) on standard EUV.
• Transitioning from IDM to Foundry: Historically an Integrated Device Manufacturer (IDM), Intel shared process rules informally with internal design teams. When developing 18A (its 2nm-class node featuring GAA and backside power), Intel initially lacked a formal Process Design Kit (PDK) for external customers, whereas 14A was built from the beginning with structured PDK maturity milestones (.5, .9, 1.0). In Q2 2026, TSMC generated $40.2B in foundry revenue compared to Intel's $5.8B and Samsung's $3.3B, with 95% of Intel Foundry's $17.8B annual revenue still coming from internal Intel products. While a SemiAnalysis roadmap suggests Intel's 14A in 2028 will match the ~240 MTr/$\text{mm}^2$ density of TSMC's N2 in 2026, Intel CTO Pushkar Ranade disputes unidimensional density metrics, noting that nodes require varied transistor types (low leakage, high drive current, SRAM, analog, and RF) and arguing that Intel and TSMC are technologically within a few percent of each other.
• Yield Management and Epitaxial Defects: Defects are caught via in-line metrology or end-of-line electrical testing followed by cross-sectioning in a Transmission Electron Microscopy (TEM) lab. A major defect focus at Intel is "epi nodules." Epitaxy flows gases over a heated wafer to grow crystal structures for the source and drain; an epi nodule is a tumor-like abnormal growth that shorts adjacent structures. Because waiting for complete data in a fab takes too long, engineers attack defects in parallel, simultaneously developing chemical cleans to remove the nodule while hunting the root cause.
• The Physics of Interconnects (Ruthenium vs. Copper) and 3D CFETs: Copper wires require a protective "liner" (glue/barrier layer) so copper adheres and does not diffuse into silicon. Because this liner cannot scale down easily, it consumes too much wire volume at tiny dimensions, driving up electrical resistance. Below a ~20-nanometer pitch (10nm metal line, 10nm dielectric), ruthenium—which can be directly etched without a liner—conducts electricity better than copper. Looking 10 to 20 years out (though clear industry visibility is only ~4 years out), chipmakers are researching Complementary Field-Effect Transistors (CFETs), which stack N-type and P-type transistors vertically to double transistor density. The primary manufacturing hurdle is the extreme aspect ratio (depth to width) required to etch deep vertical trenches and fill them with metal without voids, alongside infant-stage thermal simulation tools needed to manage heat in 3D logic stacks.
• The Area-vs-Perimeter Bottleneck and Hybrid Bonding: Modern AI processors (such as Nvidia's Blackwell, combining 2 processor dies and 8 HBM stacks) are bottlenecked by data movement between chips: doubling a die's length and width quadruples its compute area but only doubles its perimeter for interconnections. Packaging evolved from side-by-side substrate wiring to 2.5D silicon interposers, to 3D solder bumps, to "hybrid bonding," which fuses exposed copper pads of two chips directly together under heat without solder bumps. While wafer-to-wafer bonding is used in CMOS image sensors, bonding two wafers with 80% yield each drops combined stack yield to 64% because good dies get paired with bad dies; thus, logic-to-logic favors chip-to-wafer bonding using pre-tested "known good dies." Interconnect pitches have shrunk from 130–150 $\mu\text{m}$ (15 years ago) to 25 $\mu\text{m}$ (today's HBM/Intel Foveros), to sub-10 $\mu\text{m}$ in Intel's lab, and down to 0.45 $\mu\text{m}$ (450 nm) in a May 2026 Applied Materials/EV Group demonstration. Because top-level wires inside a chip are 0.5 to 1.0 $\mu\text{m}$, sub-0.5 $\mu\text{m}$ hybrid bonding allows engineers to strip off top metal layers and connect the lower internal layers of two chips directly, reducing voltage (IR) drop and picojoules per bit.
• Fab Scale Economics and the AI Supply Chain Ceiling: Roughly 80% of a semiconductor fab's cost structure is fixed, creating extreme scale economics where small yield gains (e.g., 60% to 70%) generate non-linear profit, and driving industry consolidation from 94 leading-edge chipmakers at 180nm (1999) down to 3 at 5nm (2020). At the macro level, ~$1B of ASML EUV tools (~3.5 tools per GW) supports ~$40B in Nvidia chips and ~$42B/year in AI lab ARR (such as Anthropic). Yet ASML builds fewer than 100 EUV machines per year and does not plan to significantly exceed that by 2030, while tool lead times sit at 18 months. Consequently, even with infinite capital, global leading-edge wafer output can at best double (2x) rather than grow 10x, breaking the historical 3x annual growth rate of AI compute. Furthermore, memory is an even tighter bottleneck, with global memory revenue surging from $92B (2023) to an estimated ~$925B (2026) after Intel sold off its NAND flash business. This scarcity is pushing the industry toward "pseudo-vertical" integration where hyperscalers fund dedicated fab capacity—exemplified by Intel partnering in April 2026 with Elon Musk on his planned "Terafab" and selling $23B of new stock in August 2026 to fund fab capacity.

Quotes

• At 0:00:09 - "easily 40 to 50% above our maximum capacity, which I've never seen before." - ASML CEO Peter Wennink (in an archival clip) illustrating the unprecedented equipment bottleneck constraining global chip supply.
• At 0:02:57 - "I think what we've learned is is that you you don't want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes, and while that, yeah, you'll be able to get that to work, you need to hit a certain schedule, and that's the schedule that your customer ultimately wants." - Chris Auth explaining the core lesson from Intel's multi-year 10nm delays.
• At 0:12:49 - "Just look at the number of materials we used to use in the '90s versus the materials today, it's probably gone up 10x. Uh and and there's a lot of innovation there, there's atomic layer depositions, you know, I mean just you're controlling atom by atom this stuff." - Chris Auth describing how materials science replaced simple geometric shrinking after Dennard scaling ended.
• At 0:14:54 - "We use backside power, that means that you actually alleviate some of the uh pitch requirements you have on the front side, and that allows you to print that directly with High-NA. TSMC has to run very tighter pitches because they don't have backside power, and they can't do that with High-NA, so they have to use double patterning EUV." - Chris Auth detailing why $400M High-NA EUV machines make economic sense for Intel's 14A architecture but not yet for TSMC.
• At 0:25:04 - "One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you've waited too long, it's already too late." - Kevin Fischer explaining the mindset required for engineers troubleshooting yield defects in a live fab.
• At 0:30:30 - "And if you can trade off that resistive liner with no liner, ruthenium starts to win. So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper, and that's roughly in the 20-nanometer pitch range..." - Jack Kavalieros explaining why copper wires are being replaced by ruthenium at atomic scales.
• At 0:38:50 - "I can deposit the film, I can look at it, I can measure it, but the moment I try to make a contact to it, nothing sticks. It could be something fundamental as simple as the adhesion of the next step in the process simply has no way to adhere to the material." - Jack Kavalieros on why promising 2D materials and lab breakthroughs often fail during fab integration.
• At 0:46:33 - "So if you can push packaging down to 0.5 microns or below, we can start, you can almost think about taking layers off the top of the die and connecting to a lower layer within the silicon to another lower layer within the silicon, right? That's really kind of where the beauty of hybrid bonding happens." - Tyler Osborn on how sub-micron hybrid bonding blurs the boundary between packaging and internal chip wiring.
• At 0:52:58 - "So in some sense we're moving from a sort of a horizontal world again to a pseudo-vertical world, where where it's like the, you know, it's it's it's not monolithically vertically integrated, but it's kind of vertically integrated, virtually vertically integrated." - Pushkar Ranade describing how AI hyperscalers are beginning to directly finance and consume dedicated foundry capacity.
• At 0:53:51 - "Probably semiconductor foundries, the scale economics is probably the purest. Uh and the reason for that is the fixed cost is just so incredibly high uh that once you build a fab, like 80% of your cost structure is fixed." - Pushkar Ranade explaining why fab utilization and marginal yield improvements drive massive financial returns.
• At 0:59:37 - "I mean, clearly, uh in hindsight, uh probably not the smartest time to sell off uh a flash memory business. There were good reasons why we did that when we did. Um clearly, you know, nobody could see this this demand, uh this this enormous demand." - Pushkar Ranade reflecting candidly on Intel divesting its NAND memory unit just before global memory revenue surged toward ~$925B.

Takeaways

• Enforce strict phase-gate maturity criteria in complex R&D: To prevent one delayed sub-component from derailing an entire product schedule, establish strict yield, defect, and performance thresholds in research; if a technology misses the gate, bump it to the next generation rather than forcing it into production.
• Use "short-loop vehicles" and tiered fast-tracking ("hot boxes") to accelerate learning: When full production cycles take a month or more across 2,000 steps, isolate variables by testing simplified unit cells (like a single diode or 1-on-1 nanoribbon stack) and reserve a strict priority tier ("Hot Box 1") to rush critical experimental lots past tool queues.
• Act in parallel before data is complete: Train engineering teams to understand business urgency so they do not wait for perfect information; when a defect like an epi nodule appears, simultaneously engineer a downstream mitigation (like a specialized chemical clean) while another team hunts the upstream root cause.
• Design for ~80% tool fungibility across product generations: When capital equipment costs hundreds of millions of dollars and has 18-month lead times, architect consecutive process nodes (such as 18A to 14A) so that roughly 80% of the factory machinery can be reused without re-tooling.
• Anchor long-term AI compute forecasts to physical equipment lead times, not capital availability: Anyone modeling AI scaling through 2030 must account for the fact that wafer supply cannot continue growing 3x annually; because toolmakers like ASML are capped near ~100 EUV units a year and sub-suppliers require years to expand, leading-edge silicon supply can at best ~2x over this window.
• Challenge "indoctrinated" infrastructure costs: With fab construction costs doubling every 4 to 5 years and individual scanners reaching $400 million, hardware leaders must question decades-old assumptions—such as whether traditional cleanroom environments and 30-year-old CPU design habits are strictly necessary for greenfield manufacturing.